Self-Aligned Planar Double-Gate Field-Effect Transistors Fabricated by a Source/Drain First Process
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概要
- 論文の詳細を見る
We introduce a new self-aligned process for fabricating planar double-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). The source/drain area is defined first by opening a trench in a silicon-on-insulator layer. In the trench, a bottom gate, a silicon channel and a top gate are stacked up by selective epitaxy, lateral solid-phase epitaxy and a damascene process, respectively. We demonstrate MOSFET operations controlled by a tied double gate and those by independently biased top and bottom gates.
- Japan Society of Applied Physicsの論文
- 2005-01-10
著者
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Huda Md.
National Institute Of Advanced Industrial Science And Technology (aist)
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ISHII Kenichi
National Institute of Advanced Industrial Science and Technology
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Sakamoto Kunihiro
National Institute Of Advanced Industrial Science And Technology (aist)
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Sakamoto Kunihiro
National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
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