Improvement of the bit-stream squarer and square root circuit based on ΣΔ modulation

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概要

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• To improve the arithmetic performance of the conventional bit-stream squarer circuit based on sigma delta (ΣΔ) modulation, the method of bit translation is proposed. In addition, the original bit-stream squarer inside the bit-stream square root circuit is replaced with the proposed bit-stream squarer to reduce the arithmetic operation error. The performances of the proposed bit-stream squarer and square root circuit were verified through the simulation in Matlab. Compared with the conventional circuits, the proposed circuits can increase the calculation accuracy signally.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Meng Qiao

  Institute of RF- & OE-ICs, Southeast University

• Liang Yong

  College of Food Science & Engineering, NanJing University of Finance and Economics

• Wang Zhigong

  Institute of RF- & OE-ICs, Southeast University

• Guo Xiaodan

  Institute of RF- & OE-ICs, Southeast University

• Zhang Changchun

  College of Electronic Science and Engineering, NanJing University of Posts and Telecommunications

• Liang Yong

  College of Food Science & Engineering, NanJing University of Finance and Economics

• Guo Xiaodan

  Institute of RF- & OE-ICs, Southeast University

関連論文

• Improvement of the bit-stream squarer and square root circuit based on ΣΔ modulation

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