An 180 nm CMOS 1.84-to-3.62 GHz fractional-N frequency synthesizer with skewed-reset PFD for removing noise-folding effect

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概要

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• To remove the noise folding effect, which is a primary cause of degradation of the close-in phase noise of fractional-N phase-locked loops (PLLs) that use sigma-delta modulation, a fractional-N frequency synthesizer for broad-band and multi-standard mobile TV tuners was designed. The proposed skewed-reset phase frequency detector (SR-PFD) provides a key solution to the problem of noise folding by enhancing the linearity of the phase frequency detection path through the charge pump (CP). Degradation of the reference spur —the unwanted effect in SR-PFDs— is blocked through the use of a sampled loop filter. An SR-PFD in a frequency synthesizer fabricated on a 180 nm CMOS process enhanced phase noise by 10 dB or more by using a multi stage noise shaper (MASH) 1-1-1 sigma-delta modulator (SDM), while a sampled loop filter decreased the amplitude of the reference spur by 7–13 dB.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Hwang In-Chul

  Integrated Circuits & Systems Lab, Kangwon National University

• Bae Sang-Geun

  Department of Electronics Engineering, Korea University

• Kim Kyeong-Woo

  Integrated Circuits & Systems Lab, Kangwon National University

関連論文

• An 180 nm CMOS 1.84-to-3.62 GHz fractional-N frequency synthesizer with skewed-reset PFD for removing noise-folding effect

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