A new dual −Gm structure with Class-AB operation of low-power low-phase-noise K-band CMOS VCO

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A low-power low-phase-noise K-band CMOS VCO with dual negative conductance (−Gm) structure for class-AB operation is proposed in this paper. By utilizing the dual −Gm structure, the negative conductance of the K-band VCO is effectively enhanced. Therefore, the severe startup condition for the K-band CMOS VCO can be alleviated, leading to reduced dc power consumption. Moreover, VCO cores operating in class-AB region exhibit enlarged voltage swings, resulting in an improved VCO phase noise. Based on the proposed architecture, the fabricated 0.18-µm CMOS VCO cores consume total 5.4-mW low dc power at 1.2-V supply voltage. At this bias condition, the measured phase noise is −106.15 dBc/Hz at 1-MHz offset from a 22.1-GHz carrier, the tuning range is 9.8%, and the output power is −7.1 dBm. Compared to the recently published K-band 0.18-µm CMOS VCOs, this work achieves low dc power consumption, low phase noise, and superior figure-of-merit (FOM).
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