Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption

スポンサーリンク

概要

• 論文の詳細を見る

• Protecting the confidentiality and integrity of a configuration bitstream is essential for the dynamic partial reconfiguration (DPR) of field-programmable gate arrays (FPGAs). This is because erroneous or falsified bitstreams can cause fatal damage to FPGAs. In this paper, we present a high-speed and area-efficient bitstream protection scheme for DPR systems using the Advanced Encryption Standard with Galois/Counter Mode (AES-GCM), which is an authenticated encryption algorithm. Unlike many previous studies, our bitstream protection scheme also provides a mechanism for error recovery and tamper resistance against configuration block deletion, insertion, and disorder. The implementation and evaluation results show that our DPR scheme achieves a higher performance, in terms of speed and area, than previous methods.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• KATASHITA Toshihiro

  Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST)

• TODA Kenji

  Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST)

• HORI Yohei

  Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST)

• SAKANE Hirofumi

  Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST)

• SATOH Akashi

  The University of Electro-Communications

関連論文

• Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption

スポンサーリンク