Wafer Level Packaging to Address Future Direct Chip Attach Needs

概要

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This paper covers results from early pathfinding investigations of a wafer level package (WLP) technology that addresses future direct chip attach (DCA) needs. An overview of the WLP technology and pathfinding results covering key process flow evaluations and future challenges to apply the concept to DCA are presented. Proof-of-concept (POC) of 300mm wafer-level mold integrating with Cu bumps was demonstrated by investigating the mold thickness uniformity, wafer warpage, and solder joint reliability on the board. We conclude with a discussion of the key risk areas remaining challenges that includes the mold grinding thickness variance control, optimization of the material properties, and alternative low cost bumping technologies scalable less than 0.3mm pitch, and outline the next steps to continue data collection on the wafer warpage behavior, the die breakage strength, and the board level assembly process using a standard surface mount infrastructure in our pathfinding work.