Electrical Test Method for Interconnect Open Defects in 3D ICs

スポンサーリンク

概要

• 論文の詳細を見る

• In this paper, an electrical test method is proposed to detect and locate open defects occurring at interconnects between two dies in 3D ICs. The test method utilizes a test architecture based on IEEE 1149.1 standards to provide a test vector to a targeted interconnect. Also, a testable design method for the IC is proposed for our testing. In this paper, testability of the electrical testing is evaluated using a SPICE simulation. The simulation results show that a resistive open defect of 100 Ω can be detected at a test speed of 1 GHz. Also, the test circuit is implemented inside a prototype IC. It is experimentally examined whether open defects between the IC and a printed circuit board can be detected by the test method. They are detected at a speed of 10 MHz by the test method in the experiments. It promises that interconnect open defects in a 3D IC can be detected by the test method per an interconnect at a test speed of at least 10 MHz.

著者

• YOTSUYANAGI Hiroyuki

  Institute of Technology and Science, The University of Tokushima

• Hashizume Masaki

  Institute of Technology and Science, The Univ. of Tokushima

• Konishi Tomoaki

  Institute of Technology and Science, The Univ. of Tokushima

• Yotsuyanagi Hiroyuki

  Institute of Technology and Science, The Univ. of Tokushima

関連論文

• Electrical Test Method for Interconnect Open Defects in 3D ICs
• Propagation Delay Analysis of a Soft Open Defect inside a TSV
• SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines

スポンサーリンク