A High Resolution and High Linearity 45 nm CMOS Fully Digital Voltage Sensor for Low Power Applications

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概要

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• This paper proposes a design of voltage sensor with new controllable delay element (CDE) having high linearity and high resolution. The proposed CDE uses power supply node to measure the voltage value. However, the delay increases exponentially at low voltage level. In this paper we add a PMOS header in parallel with the conventional CDE to compensate the delay degradation at lower voltage. We develop a 16-levels fully digital voltage sensor with a voltage range of 0.8 ∼ 1.1 V and 20 mV resolution by using of the proposed delay elements. The proposed circuit is designed and simulated in 45 nm CMOS process. The simulation results show the feasibility of the high resolution and high linearity at low voltage by using of the proposed delay elements.

著者

• RYU Myunghwan

  UNIST

• KIM Youngmin

  UNIST

関連論文

• TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC
• A High Resolution and High Linearity 45 nm CMOS Fully Digital Voltage Sensor for Low Power Applications
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• TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC

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