A low latency semi-systolic multiplier over <I>GF</I>(2<I>m</I>)

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概要

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• A finite field multiplier is commonly used in implementations of cryptosystems and error correcting codes. In this paper, we present a low latency semi-systolic multiplier over <I>GF</I>(2<I>m</I>). We propose a finite field multiplication algorithm to reduce latency based on parallel computation. The proposed multiplier saves at least 31% time complexity as compared to the corresponding existing structures.

著者

• Kim Kee-Won

  College of Engineering, Dankook University

• Kim Seung-Hoon

  Department of Multimedia Engineering, Dankook University

関連論文

• A low latency semi-systolic multiplier over GF(2m)

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