Efficient verification of IP watermarks in FPGA designs through lookup table content extracting

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概要

• 論文の詳細を見る

• Digital watermarking is an innovative technique for intellectual property protection (IPP) of Field Programmable Gate Array (FPGA) designs. However, many of these techniques usually need manually extract marks from binary bit-files by the FPGA tool or exhaustive search to find out marks in the design, which results in inefficiency of the watermark verification. This paper presents a method to fast verify the authorship through extracting the content of the watermarked lookup tables from a binary bit-file. We demonstrate the proposed method on several Xilinx Virtex-II devices, and experimental results on the watermarked designs from the IWLS 2005 benchmarks show that the verification of authorship has high efficiency.

著者

• LIN Yaping

  College of Information Science and Engineering in Hunan University

• Che Wenjie

  College of Information Science and Engineering, Hunan University

• Zhang Jiliang

  College of Information Science and Engineering, Hunan University

• Wu Qiang

  College of Information Science and Engineering, Hunan University

• Lu Yongqiang

  Research Institute of Information Technology, Tsinghua University

• Zhao Kang

  Intel Corporation

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