Design of low power fixed-width multiplier with row bypassing

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概要

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• This paper presents a low power fixed-width multiplier with row bypassing (FWM-RB) for multimedia applications. When the operands of the multiplier are zero, significant power reductions can be achieved if that particular row is disabled. This is done with the help of multiplexers incorporated in the Modified Full Adder (MFA). The design is developed by using Verilog-HDL and implemented using Cadence typical libraries of TSMC 90nm technology with a supply voltage of 1.2V. This work evaluates the performance of power, area and delay of fixed-width multipliers and it has been shown that the proposed architecture consumes lesser power as compared to the conventional fixed-width multipliers.

著者

• Mallick P.S.

  School of Electrical Engineering, VIT University

• Ghosh Sneha

  School of Electrical Engineering, VIT University

• Balamurugan S.

  School of Electrical Engineering, VIT University

• Balakumaran S.

  School of Electrical Engineering, VIT University

• Marimuthu R.

  School of Electrical Engineering, VIT University

関連論文

• Design of low power fixed-width multiplier with row bypassing

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