FPGA realization of Inverse Discrete Wavelet Transform

概要

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Lifting Scheme based 2-D Inverse Discrete Wavelet Transform 2-D (IDWT) core for JPEG 2000 is implemented into FPGA following a new approach of reusing hardware components. The approach leads towards higher area efficiency and speed optimization. Design realized by Le-Gall 5/3 filter, achieved significant acceleration that executes at over 300MHz with 7.13Msamples throughput whereas using less than 1% of logic elements in Altera Stratix II FPGA. High quality reconstructed image are extracted from Matlab and VHDL simulations. Implementation details of the individual hardware blocks, synthesis result, and performance analysis are presented.