Noise margin and short-circuit current in FGMOS logics
スポンサーリンク
概要
- 論文の詳細を見る
Even when floating-gate logics are very-low-voltage circuits, as power supply is reduced, large fan-in FGMOS gates are prone to fail. Thus, determining the negative impact of noise margin and short-circuit current in this type of circuits is crucial to achieve optimal operation for a particular application. For this reason, a systematic and reliable technique for obtaining the correlation between fan-in and supply voltage, simultaneously considering noise margin and short-circuit current, is proposed.
論文 | ランダム
- 緊張病症状で始まった脳炎の一例
- アイリス認識技術とその応用 (特集 最近のほんもの確認技術)
- 栽培ヒエの農業形質および成分・品質の系統間変異とその相互関係
- 日鉄争議〔現地報告〕
- 宣教師の日本語学習--アメリカン・ボードの場合