Noise margin and short-circuit current in FGMOS logics
スポンサーリンク
概要
- 論文の詳細を見る
Even when floating-gate logics are very-low-voltage circuits, as power supply is reduced, large fan-in FGMOS gates are prone to fail. Thus, determining the negative impact of noise margin and short-circuit current in this type of circuits is crucial to achieve optimal operation for a particular application. For this reason, a systematic and reliable technique for obtaining the correlation between fan-in and supply voltage, simultaneously considering noise margin and short-circuit current, is proposed.
論文 | ランダム
- 2p-H-3 散逸捕捉イオン不安定性における軌道効果
- 11p-Q-9 散逸捕捉イオン不安定性における有限ベータ効果
- 11p-Q-6 有限バナナ幅効果を考慮した実効電場
- 30a-SB-4 捕捉イオン不安定性のモデル方程式の微視的導出 I
- 30p-Pβ-6 Tokamak Ignition Approach by Spot Model