Noise margin and short-circuit current in FGMOS logics
スポンサーリンク
概要
- 論文の詳細を見る
Even when floating-gate logics are very-low-voltage circuits, as power supply is reduced, large fan-in FGMOS gates are prone to fail. Thus, determining the negative impact of noise margin and short-circuit current in this type of circuits is crucial to achieve optimal operation for a particular application. For this reason, a systematic and reliable technique for obtaining the correlation between fan-in and supply voltage, simultaneously considering noise margin and short-circuit current, is proposed.
論文 | ランダム
- eCTDの最近の動向
- 臨床開発・薬事職のための英語翻訳の基礎(Season 2 第6回)否定表現の訳し方
- Process Validation:General Principles and Practices Revision 1の解釈 (特集 GMP査察の動向と規制の解釈)
- 最近のFDA Warning Letterに見る特徴と日本の課題 (特集 GMP査察の動向と規制の解釈)
- 特集 GMP査察の動向と規制の解釈