A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition

概要

論文の詳細を見る
This paper describes a SIFT (Scale Invariant Feature Transform) descriptor generation engine which features a VLSI oriented SIFT algorithm, three-stage pipelined architecture and novel systolic array architectures for Gaussian filtering and key-point extraction. The ROI-based scheme has been employed for the VLSI oriented algorithm. The novel systolic array architecture drastically reduces the number of operation cycle and memory access. The cycle counts of Gaussian filtering module is reduced by 82%, compared with the SIMD architecture. The number of memory accesses of the Gaussian filtering module and the key-point extraction module are reduced by 99.8% and 66% respectively, compared with the results obtained assuming the SIMD architecture. The proposed schemes provide processing capability for HDTV resolution video (1920 × 1080 pixels) at 30 frames per second (fps). The test chip has been fabricated in 65nm CMOS technology and occupies 4.2 × 4.2mm2 containing 1.1M gates and 1.38Mbit on-chip memory. The measured data demonstrates 38.2mW power consumption at 78MHz and 1.2V.