A Design Procedure for CMOS Three-Stage NMC Amplifiers

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概要

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• This paper presents a novel time-domain design procedure for fast-settling three-stage nested-Miller compensated (NMC) amplifiers. In the proposed design methodology, the amplifier is designed to settle within a definite time period with a given settling accuracy by optimizing both the power consumption and silicon die area. Detailed design equations are presented and the circuit level simulation results are provided to verify the usefulness of the proposed design procedure with respect to the previously reported design schemes.

著者

• YAVARI Mohammad

  Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of

関連論文

• A Design Procedure for CMOS Three-Stage NMC Amplifiers

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