A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840×2160@60fps decoding at less than 133MHz, with 37.2k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 4×4 block to DRAM.
論文 | ランダム
- 老年期における不安とうつ
- 演題20. 円形脱毛症のbiofeedback療法(2)(第23回日本バイオフィードバック学会総会演題抄録)(一般発表)
- 線路上空建築物の中高層化に対応した設計法
- 21370 高架橋-旅客上家間の相互作用を考慮した応答性状に関する研究 : (その3)上家の構造特性が連成挙動に与える影響(構造物の応答制御,構造II)
- 演題19. 円形脱毛症のbiofeedback療法(1)(第23回日本バイオフィードバック学会総会演題抄録)(一般発表)