Adaptive Circuits for the 0.5-V Nanoscale CMOS Era
スポンサーリンク
概要
- 論文の詳細を見る
The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, ΔVt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for Vt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.
論文 | ランダム
- 23aRD-2 全光学的手法によるBEC生成に向けた低速原子源開発(23aRD 量子エレクトロニクス(冷却原子),領域1(原子・分子,量子エレクトロニクス,放射線物理))
- 23aRD-1 一次元光格子中の冷却原子のローディング(23aRD 量子エレクトロニクス(冷却原子),領域1(原子・分子,量子エレクトロニクス,放射線物理))
- Development of a multi-layered virtual tooth model for the haptic dental training system
- Thoracic Disk Herniation Manifesting as Sciatica-Like Pain : —Two Case Reports—
- Effects of Low-dose Heavy Ions on the Postnatal Development of Mice and the Yield of White Spots in the Mid-ventrum and Tail-tips