Novel FPGA-based pipelined floating point FFT processor

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概要

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• Two novel architectures for pipelined floating point fast Fourier transform on FPGA are presented. The new radix-22 two-path delay feedback (R22TDF) architecture leads to 50% area saving for floating point complex adders compared with the radix-22 single-path delay feedback (R22SDF) architecture. Besides a new hybrid architecture is presented which mixes the R22TDF and R22TDF butterfly structures and is flexible and efficient for FPGA implementation.

著者

• Wei Li

  School of Electronics and Information Engineering, Beijing University of Aeronautics and Astronautic

• Jun Wang

  School of Electronics and Information Engineering, Beijing University of Aeronautics and Astronautic

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