A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme

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概要

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• A digital phase corrector is proposed to reduce the time jitter noise in a high speed parallel chip-to-chip interface system with a quad data rate (QDR) input/output (I/O) scheme. The proposed digital phase corrector for the 4-phase clock utilizes only one duty cycle detector by using a digitally controlled phase correction method and multiplexing function of transmitter for a QDR I/O scheme. Also, it reduces the static phase error generated in the transmitter, because of the inclusion of a replica of the transmitter in the feedback loop. To verify the proposed digital phase correction scheme, a digital phase corrector for the QDR I/O scheme with a 1.25GHz 4-phase clock was designed by using a 70nm 3-metal CMOS process with a 1.35V supply. The current consumption and phase correction range were 2.73mA and ±8%, respectively.

著者

• Jang Young-Chan

  School of Electronic Engineering, Kumoh National Institute of Technology

• Jang Young-chan

  School Of Electronic Engineering Kumoh National Institute Of Technology

関連論文

• A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme
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