Low complexity pipeline FFT processor for MIMO-OFDM systems

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概要

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• In this paper, we propose a low complexity pipeline FFT processor for MIMO-OFDM systems with four transmitting and four receiving (4 × 4) antennas. The proposed FFT processor is based on multi-channel structure which enables to support multiple data streams efficiently. With mixed-radix algorithm, the number of non-trivial multiplications of the proposed FFT processor are decreased. Implementation results show that the proposed FFT processor reduces the required number of logic gates by 25% over the conventional 4-channel R4MDC FFT processor which has been considered to be the most area-efficient FFT processor for 4 × 4 MIMO-OFDM systems.

著者

• Kim Jaeseok

  School of Electrical and Electronic Engineering, Yonsei University

• Jung Yunho

  Institute of TMS Information Technology, Yonsei University

• Lee Sangmin

  School of Electrical and Electronic Engineering, Yonsei University

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• Low complexity pipeline FFT processor for MIMO-OFDM systems

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