Adiabatic quasi 6T-SRAM with shared writing and reading ports
スポンサーリンク
概要
- 論文の詳細を見る
An adiabatic quasi 6T-SRAM is proposed in which a memory cell shares the writing and reading ports between a flip-flop and a bit line so that the transistor number in a memory cell is decreased to about six. The gradual charging operation in the circuit can avoid electromigration and hot carrier effects. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually by using a high-resistivity nMOSFET, and the nMOSFET is turned off to set the memory cell power line in a high-impedance state. Then, adiabatic signal from the shared writing port is input to charge the memory cell power line to VDD. In the reading mode, the shared reading port, which connects the flip-flop and the bit line, is used for stable operation. The bit line can be precharged to a small value (for example, VDD/4), which enables a small current flow during the reading mode. Logic data are read by sensing the voltage decrease in the precharged bit line.
論文 | ランダム
- 階段昇降の観察から治療介入の手がかりを得た症例
- 階段昇降速度規定時,非規定時の心拍数変化の検討
- 欧州における福祉・医療関連機器の研究開発 : その3, 応用研究編(階段昇降支援装置)
- 619 住宅の力学環境評価手法に関する研究 : その7 階段昇降における加速度と感性評価との関係(建築計画)
- 大同工業/階段昇降機は家族の願い叶える (特集/適切な福祉用具を適切な人に(3号連続総合テーマ)--福祉用具の日とHCRを控えて) -- (ケアマネさんにこう伝えたい)