Residual stress evaluation in resin-molded IC chips using finite element analysis and piezoresistive gauges

概要

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The high residual stress in a resin-molded electronic package sometimes makes the electronic functions unstable. Therefore the residual stress in electronic packages, especially on the top surfaces of semiconductor chips, should be evaluated. The objective of this study is to present a simple method for evaluating residual stress in resin-molded semiconductor chips using a combination of experimental and numerical methods. The actual residual stress of the packaging process was measured by using test chips that included piezoresistive gauges. A linear thermoelastic finite element analysis was then carried out using a three-dimensional model. The finite element analysis was performed under a stress-free temperature determined by the temperature dependence of the residual stress, which was experimentally measured by using the piezoresistive test chips. The measured residual stress using the test chips agreed well with the results of the finite element analysis. It was therefore confirmed that the present evaluation method, combining experimental and numerical methods, is reliable and reasonable.