Simulation and 18 Gb/s testing of a data-driven self-timed RSFQ demultiplexer
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概要
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We have developed a Data Driven Self-Timed (DDST) Rapid-Single-Flux-Quantum (RSFQ) demultiplexer (demux) for the interface between on-chip high-speed RSFQ circuits and off-chip low-speed circuits. In order to eliminate the timing issue in a synchronous clocking system we employed the DDST architecture, where a clock signal is localized within a 2-bit basic demur module and dual rail lines are used to transfer the timing information between the modules. A larger demur can be produced simply by connecting the 2-bit modules in a tree structure. The DDST demur was designed for 10 Gb/s operation with sufficient de bias margin using HYPRES 1 kA/cm(2) Nb process. We have successfully tested operation of the 2-bit demur up to 18 GHz using the DDST on-chip high-speed test system which was developed in our group.
- Institute of Electrical and Electronics Engineersの論文
Institute of Electrical and Electronics Engineers | 論文
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