A 2K-Gate GaAs Gate Array with a WN Gate Self-Alignment FET Process

概要

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A 2K-gate DCFL GaAs gate array has been successfully fabricated with a WN gate self-alignment GaAs MESFET process. Chip size was 4.59 mm×4.73 mm. A basic cell, consisting of one DFET and three EFET's, can be programmed as an inverter or a two or three-INPUT NOR gate by personalizing with first- and second-level interconnection and via hole masks. The I/O buffer was implemented with a large DCFL push-pull circuit. The unloaded propagation delay time was 42 ps/gate at a power dissipation of 0.5 mW/gate. The increases in delay time due to various loading capacitances were 11-ps/fan-in, 16-ps/fan-out, 59-ps/1-mm interconnection and 0.95 ps/crossover (area: 2 μm×3 μm). An 8×8-bit parallel multiplier was fabricated on this gate-array chip. A multiplication time of 8.5 ns was achieved at a power dissipation of about 400 mW including I/O buffers.
Institute of Electrical and Electronics Engineers (IEEE)の論文
1985-10-00