Design techniques for switched capacitor adaptive line equlizer
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概要
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Design techniques are described for a switched capacitor adaptive line equalizer which is applied to high-speed (200 kb/s) digital transmission over analog subscriber loops. An equalizer transfer function is approximated so as to minimize intersymbol interference of an isolated pulse response. Optimum pole-zero location, which is suited to line characteristics in a wide frequency band, is also discussed. In order to attain high accuracy capacitor ratios using a small unit capacitor, capacitor values are rounded off into equivalent integer values, and are discretely optimized using pole-zero deviation as an error criterion. The equalizer has a finite number of frequency responses which correspond to line lengths. Gain and delay time differences between the adjoining step responses are compressed. The switched capacitor line equalizer was fabricated using 3- mu m CMOS technology. Measured data were very close to designed performances.
- Institute of Electrical and Electronics Engineers (IEEE)の論文
- 1985-08-00
Institute of Electrical and Electronics Engineers (IEEE) | 論文
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