An FPGA Implementation of the Progressive Tree Neighborhood Algorithm : Phylogenetic Tree Reconstruction with Maximum Parsimony

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概要

• 論文の詳細を見る

• In this paper, we present an FPGA-hardware implementation for the progressive tree neighborhood algorithm applied to phylogenetic tree reconstruction with maximum parsimony. The proposed hardware architecture is modular, and has pipelined stages to improve the performance and reduce the execution time of the algorithm. Implementation results for a specific problem showed a 1247x acceleration compared to a C++ software implementation.

• 一般社団法人電子情報通信学会の論文
• 2013-05-13

著者

• Maruyama Tsutomu

  筑波大学システム情報工学研究科

• Block Henry

  筑波大学システム情報工学研究科

関連論文

• An FPGA Implementation of the Progressive Tree Neighborhood Algorithm : Phylogenetic Tree Reconstruction with Maximum Parsimony

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