High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC(System Level Design,<Special Section>VLSI Design and CAD Algorithms)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes a flexible VLSI architecture design for motion estimation in H.264/AVC using a high-efficiency variable block-size decision (VBSD) approach. The proposed VBSD approach can perform a full motion search on integrating the 4×4 block sizes into 4×8, 8×4, 8×8, 8×16, 16×8, or 16×16 block sizes and then appropriately select the optimal modes for motion compensation operating. In other words, the proposed architecture based on the VBSD approach can effectively reduce the encoding time of the motion estimation by dealing with different block sizes under 16×16 searching range. Using the TSMC 0.18-μm CMOS technology, the proposed architecture has been successfully realized. Simulation and verification results show that the proposed architecture has significant bit-rate reduction and small PSNR degradation. Also, the physical chip design revealed that the maximum frame rate of this work can process 704fps with QCIF (176×144), 176fps with CIF (352×288) and 44fps with 4CIF (704×576) video resolutions under lower gate counts and higher working frequency.

• 2007-12-01

著者

• HSU Chun-Lung

  Department of Electrical Engineering, National Dong Hwa University

• HO Mean-Hom

  Department of Electrical Engineering, National Dong Hwa University

• Hsu Chun-lung

  Department Of Electrical Engineering National Dong Hwa University

• Ho Mean-hom

  Department Of Electrical Engineering National Dong Hwa University

関連論文

• High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC(System Level Design,VLSI Design and CAD Algorithms)
• Design of High-Performance Charge-Pump Circuit for PLL Applications(Analog Design)(VLSI Design and CAD Algorithms)

スポンサーリンク