Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs(System Level Design,<Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• FPGA-based hardware emulators are often used for the verification of LSI functions. They generally have dedicated external memories, such as SDRAMs, to compensate for the lack of memory capacity in FPGAs. In such a case, access between the FPGAs and the dedicated external memory may represent a major bottleneck with respect to emulation speed since the dedicated external memory may have to emulate a large number of memory blocks. In this paper, we propose three methods, "Dynamic Clock Control (DCC)," "Memory Mapping Optimization (MMO)," and "Efficient Access Scheduling (EAS)," to avoid this bottleneck. DCC controls an emulation clock dynamically in accord with the number of memory accesses within one emulation clock cycle. EAS optimizes the ordering of memory access to the dedicated external memory, and MMO optimizes the arrangement of the dedicated external memory addresses to which respective memories will be emulated. With them, emulation speed can be made 29.0 times faster, as evaluated in actual LSI emulations.

• 社団法人電子情報通信学会の論文
• 2007-12-01

著者

• Hosokawa Kohei

  Nec System Ip Core Research Laboratories

• TANAKA Katsunori

  NEC System IP Core Research Laboratories

• NAKAMURA Yuichi

  NEC System IP Core Research Laboratories

関連論文

• Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs(System Level Design,VLSI Design and CAD Algorithms)

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