Long-Point FFT Processing Based on Twiddle Factor Table Reduction(VLSI Design Technology and CAD)

概要

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In this paper, we present a new fast Fourier transform (FFT) algorithm to reduce the table size of twiddle factors required in pipelined FFT processing. The table size is large enough to occupy significant area and power consumption in long-point FFT processing. The proposed algorithm can reduce the table size to half, compared to the radix-2^2 algorithm, while retaining the simple structure. To verify the proposed algorithm, a 2048-point pipelined FFT processor is designed using a 0.18μm CMOS process. By combining the proposed algorithm and the radix-2^2 algorithm, the table size is reduced to 34% and 51% compared to the radix-2 and radix-2^2 algorithms, respectively. The FFT processor occupies 1.28mm^2 and achieves a signal-to-quantization-noise ratio (SQNR) of more than 50dB.
社団法人電子情報通信学会の論文
2007-11-01