Implementations of Low-Cost Hardware Sharing Architectures for Fast 8×8 and 4×4 Integer Transforms in H.264/AVC(Digital Signal Processing)

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概要

• 論文の詳細を見る

• In this paper, novel hardware sharing architectures are proposed for realizations of fast 4×4 and 8×8 forward/inverse integer transforms in H.264/AVC applications. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (1-D) 4×4 and 8×8 forward/inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need a smaller number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 4×4 and individual 8×8 integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures can process up to 125MHz with the cost-effective area and are suitable for VLSI implementations to accomplish the H.264/AVC signal processing.

• 社団法人電子情報通信学会の論文
• 2007-02-01

著者

• Fan Chih‐peng

  Department Of Electrical Engineering National Chung Hsing University

• Fan Chih-peng

  Department Of Electrical Engineering National Chung Hsing University

• Fan Chih-peng

  Department Of Electrical Engineering National Cheng Kung University

• LIN Yu-Lian

  Department of Electrical Engineering, National Chung Hsing University

• Lin Yu-lian

  Department Of Electrical Engineering National Chung Hsing University

関連論文

• Implementations of Low-Cost Hardware Sharing Architectures for Fast 8×8 and 4×4 Integer Transforms in H.264/AVC(Digital Signal Processing)
• Fast 2-Dimensional 8×8 Integer Transform Algorithm Design for H.264/AVC Fidelity Range Extensions(Image Processing and Video Processing)
• Centralized Fast Slant Transform Algorithms
• Fast Algorithm Designs for Low-Complexity 4×4 Discrete Cosine Transform(Digital Signal Processing)

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