An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model(VLSI Design Technology and CAD)

スポンサーリンク

概要

• 論文の詳細を見る

• Embedded memories have been used extensively in modem SoC designs. In order to estimate the power consumption of an entire design correctly, an accurate memory power models are needed. However, the memory power model that is commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. In this work, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effects with scaling capability. The proposed approach is very useful to be combined with the memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the proposed dummy modular approach can link our enhanced memory power model into the existing power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.

• 社団法人電子情報通信学会の論文
• 2007-05-01

著者

• Yu Chi-chia

  National Central University

• Chiu Yi-fang

  Soc Technology Center Of The Industrial Technology Research Institute

• Liu Chien-nan

  National Central University

• HSIEH Wen-Tsan

  National Central University

関連論文

• An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model(VLSI Design Technology and CAD)

スポンサーリンク