A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector(<Special Section>Analog Circuit and Device Technologies)

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概要

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• A clock and data recovery (CDR) circuit using a new half-rate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-μm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120ps and 170ps, respectively, while operating at the input data rate of 1Gb/s. The total power dissipation of the CDR is 64.8mW for the supply 3V.

• 社団法人電子情報通信学会の論文
• 2006-06-01

著者

• Yang Ching‐yuan

  National Chung Hsing Univ. Taichung Twn

• Lee Yu

  Soc Technology Center (stc) Industrial Technology Research Institute (itri)

• YANG Ching-Yuan

  Faculty of National Chung Hsing University

• LEE Cheng-Hsing

  Winbond Electronics Corp.

関連論文

• A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector(Analog Circuit and Device Technologies)

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