高効率を追求した半導体ウェハテスト工程の評価

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概要

• 論文の詳細を見る

• Many semiconductor device memories have tremendously important roles and have been used in a wide range of modern electrical products. For exaple flash memory that can be electrically erased, is non-volatile and can be reprogrammed.lt is used for general storage and the transfer of data between computers and many digital products and has become the dominant from of technology. On the other hand, from the view point of manufacturing flash memory, the testing production process is complicated because of the longer test time and large amount of test equipments rather than other memories (DRAM, SRAM etc.). This paper describes evaluating wafer test process for flash memory to increase the rate of tester operation and realizing flash memory devices on the appointed date of delivery. The main contributions of this paper are three fold: (1) the sophisticated modeling of complicated wafer testing processes and application of Erlang distribution for management of wafer lots, (2) the proposed scheduling algorithm of test equipments for wafer testing, (3) the development of dedicated simulator involved many practical production parameters of fully test processes. The key results of this paper can be summarized as follows: (1) The complicated testing processes was successfully modeled using a simplification wafer testing process. The Erlang distribution enables one to define dumpling states (coarseness and minuteness) at work in hands of wafer testing. (2) The procedure of scheduling algorithm is consisted of both using plural test equipments simultaneously and maximizing ratio of operation. The proposed algorithm verifies effectiveness of separation of wafer lots for high performance manufacturing. (3) The developed simulator is performed using practical parameters such as test time, interval times for change kits. The results of simulation promise to reduce a number of test equipments and to increase a rate of tester operation.

• 徳島文理大学の論文

著者

• 多田 哲生

  徳島文理大学大学院工学研究科

• 奥村 憲三

  シャープ株式会社avシステム事業本部:徳島文理大学大学院工学研究科

• 奥村 憲三

  徳島文理大学工学研究科

関連論文

• 半導体ウェーハテスト工程の納期を改善する手法と評価(集積エレクトロニクス)
• シミュレーションによるLSIゲート酸化膜破壊の特性評価(LSIのテスト・評価技術)
• 高効率を追求した半導体ウェハテスト工程の評価
• 徳島文理大学理工学部電子情報工学科多田研究室

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