A 256-Element Associative Parallel Processor(Special Issue on the 1994 VLSI Circuits Symposium)

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概要

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• A 256-element associative processing chip is designed for pixel-parallel image processing and machine vision applications. A five-transistor three-state dynamic memory cell is used, and each processing element has 64 trits of memory. Other processing element components include a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. These are implemented with compact circuits designed within memory pitch constraints. The chip was fabricated in a double-poly CCD-CMOS process and characterized as fully functional. A sample image processing application is demonstrated on a four-chip prototype system.

• 社団法人電子情報通信学会の論文
• 1995-06-25

著者

• Sodini Charles

  Department Of Electrical Engineering And Computer Science Massachusetts Institute Of Technology

• Herrmann Frederick

  Mit Lincoln Laboratory

関連論文

• A 256-Element Associative Parallel Processor(Special Issue on the 1994 VLSI Circuits Symposium)

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