High Capacitance Density in a Ta_2O_5 Folded Capacitor Chip

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概要

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• By folding Ta_2O_5 dielectric material into layer arrangements, the charge-storage area of a folded capacitor chip could be easily enhanced. Different from the stack and trench capacitors, such folding configuration could offer a simple geometric structure for lithographic patterning to ensure high quality of the step coverage for each layer. In this study, the capacitance density above 30fF/μm^2 could be obtained by depositing three folded Ta_2O_5 dielectric material layers separated by 15nm from each other. The breakdown electric field of a folded capacitor was nearly independent of the layer number. However, the leakage current density was enhanced with increasing number of folding layers because more convex folding corners are first to break down, providing conducting paths for leakage current. The annealing temperature should not exceed 600℃ because TiN barrier layer failed to prevent the diffusion of aluminum metal into Ta_2O_5 films above this temperature. [DOI: 10.1143/JJAP.41.1311]

• 社団法人応用物理学会の論文
• 2002-03-15

著者

• Horng Jui-hong

  Department Of Mechanical And Marine Engineering National Taiwan Ocean University

• Wang Yeong-her

  Institute Of Microelectronics Department Of Electrical Engineering National Cheng Kung University

• Houng Mau-phon

  Institute Of Microelectronics Department Of Electrical Engineering National Cheng Kung University

• HORNGI Jui-Hong

  Department of Mechanical and Marine Engineering, National Taiwan Ocean University

• HSIANG Sung-Jen

  Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University

• Horngi Jui-hong

  Department Of Mechanical And Marine Engineering National Taiwan Ocean University

• Hsiang Sung-jen

  Institute Of Microelectronics Department Of Electrical Engineering National Cheng Kung University

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