Frequency-Scaling Approach for Managing Power Consumption in NOCs(<Special Section>VLSI Design and CAD Algorithms)

概要

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This work presents a frequency-scaling low-power (FSLP) design methodology for managing power consumption of cores in the tile-based network-on-chip (NOC) architecture. A moving picture experts group (MPEG) core is tested using the field-programmable gate array (FPGA) implementation to verify the feasibility of the proposed method. Measurement results show that about 30% power consumption can be saved in the MPEG core and reveal that the proposed FSLP design method can be suitable for cores in the tile-based NOC applications.
社団法人電子情報通信学会の論文
2005-12-01