Passivation of InP-Based Heterostructure Bipolar Transistors in Relation to Surface Fermi Level
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概要
- 論文の詳細を見る
The effect of surface Fermi level position on dc-characteristics of InP-based heterostructure bipolar transistors (HBT) is reported. The Fermi level of an InP surface covered with silicon oxide was located at an energy position close to the conduction band minimum of InP. This implies that an electron accumulation layer forms at the interface, which acts as a surface leakage path. The HBT passivated with silicon oxide films showed large excess base current and poor current gain. In contrast, the Fermi level position at the silicon nitride/InP interface was found to be near the midgap, and no electron accumulation layer was formed at the interface. The HBT passivated with silicon nitride film showed excellent dc characteristics with very small, excess base current.
- 社団法人応用物理学会の論文
- 1999-02-28
著者
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Kikawa Takeshi
Central Research Laboratory, Hitachi Ltd.
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TAKATANI Shinichiro
Central Research Laboratory, Hitachi, Ltd.
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Kikawa Takeshi
Central Research Laboratory Hitachi Ltd.
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MASUDA Hiroshi
Central Research Laboratory, Hitachi, Ltd.
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TANOUE Tomonori
Central Research Laboratory, Hitachi, Ltd.
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Tanoue Tomonori
Central Research Laboratory Hitachi Ltd.
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Takatani Shinichiro
Central Research Laboratory Hitachi Ltd.
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Masuda Hiroshi
Central Research Laboratory Hitachi Ltd.
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