Size Effect on Thermal Conduction in Silicon-on-Insulator Devices under Electrostatic Discharge (ESD) Conditions

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概要

• 論文の詳細を見る

• Previous experimental work has shown degradation in the electrostatic discharge (ESD) failure voltage for silicon-on-insulator (SOI) devices compared to that of devices made from btulk silicon substrates. Understanding of this trend requires simulations of temperature fields in SOI devices using accurate thermal property values. The present work predicts the in-plane lattice thermal conductivity of thin silicon films at temperatures up to 1000 K considering the size effect due to phonon-boundary scattering. For silicon layers thinner than 0.2 μm, a significant reduction in the thermal conductivity is expected even at temperatures as high as 700 K. A compact expression for the thermal conductivity of thin silicon films can be readily tused in device simulations. Temperature field predictions for a simplified SOI device show the impact of the size effect and motivate discussion of its implications for ESD buffer design.

• 社団法人応用物理学会の論文
• 1997-06-15

著者

• Goodson Kenneth

  Department of Mechanical Engineering Stanford University

• JU Yongho

  Department of Mechanical Engineering, Stanford University

• Ju Yongho

  Department Of Mechanical Engineering Stanford University

関連論文

• TED-AJ03-427 MODELING AND SIMULATION OF THERMOMECHANICAL NANO-INDENTATION IN POLYMER
• Size Effect on Thermal Conduction in Silicon-on-Insulator Devices under Electrostatic Discharge (ESD) Conditions
• Effect of Resistance Drift on the Activation Energy for Crystallization in Phase Change Memory

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