Josephon NOR Decoder Circuit for Josephson Memory Arrays

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概要

• 論文の詳細を見る

• A new type of Josephson decoder circuit has been devised and designed. The fundamental operation principles for the circuit are based on modification of the address signal multiplicand A_0・A_1・...A_n to NOR form. Implementation of this principle gives large operation margins and high operation speed. In building the decoder, a new large fan-out gate, inverter circuit and timed bias circuit were devised. Proper operation of the decoder was confirmed by computer simulations, and the operation times for the 5-to-32 decoder obtained were about 300 ps for nominal conditions and 50 ps for the best conditions. The designed operation bias margin for the decoder is ±37%.

• 社団法人応用物理学会の論文
• 1984-08-20

著者

• Fujita Shuichi

  Atsugi Electrical Communication Laboratory Ntt

• NAKANISHI Takuji

  Atsugi Electrical Communication Laboratory, NTT

• Nakanishi Takuji

  Atsugi Electrical Communication Laboratory Ntt

関連論文

• Josephson Single-Input Self-Gating and Circuits
• Josephon NOR Decoder Circuit for Josephson Memory Arrays

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