Surface Passivation of Thin Silicon Solar Cells Using Silicon-on-Insulator Wafer
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概要
- 論文の詳細を見る
Solar cells with various cell thicknesses were fabricated using silicon-on-insulator (SOI) wafers, and effects of applied bias voltages (V_B) at the SOI layer/SiO_2 back interface on cell performance were investigated. A surface passivation effect was obtained by applying negative V_B to accumulate holes at the interface. Both open-circuit voltage (V_<oc>) and short-circuit current were improved by applying negative V_B. This effect becomes more dominant for thinner cells. V_<oc> of 20- and 50-μm-thick cells at V_B=-15 V increased compared to that of a 100-μm-thick cell. Surface recombination velocity (S) was estimated from the dependence of internal quantum efficiency on cell thickness. It was found that S decreased from about 10^6 to 10^4 cm・s^<-1> when V_B changed from 0 to -15 V. The improvement of cell performance by V_B was due to this reduction in S. Therefore, the surface passivation by applying bias voltages is noted as an important technique to realize high-efficiency thin silicon solar cells.
- 社団法人応用物理学会の論文
- 1995-12-15
著者
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TAKATO Hidetaka
National Institute of Advanced Industrial Science and Technology (AIST)
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Sekigawa Toshihiro
Electron Devices Division Electrotechnical Laboratory
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Sekigawa Toshihiro
Electroinformatics Group Nanoelectronics Research Institute National Institute Of Advanced Industria
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TAKATO Hidetaka
Electrotechnical Laboratory
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Sekigawa T
Electron Devices Division Electrotechnical Laboratory
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Takato H
National Institute Of Advanced Industrial Science And Technology (aist)
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