センサ面上での2次元動きベクトル検出の提案と設計

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概要

• 論文の詳細を見る

• A high speed 2-D motion vector detection on CMOS sensor focal plane is proposed. Edge detection circuit composed of two crossed differencial OTAs with time-multiplexed sampling is adopted for getting horizontal and vertical edges. 4-bits short-time digital memory is designed by transmission gate array, which can keep edge information by a smaller layout area. High speed block matching is designed by a Local Parallel and Global Collumn Parallel (LPGCP) processing architecture, which makes use of the parallel nature of images. The size of block for matching is reduced to 2×2 pixels and a search area of (±1,±1) pixels at a high frame rate, such as 1000 frames/sec. Experimental results of pixel circuit with PD, edge detection and memory are given.

• 社団法人映像情報メディア学会の論文
• 1998-12-20

著者

• HATORI Mitsutoshi

  Faculty of National Institute of Informatics

• Zheng Li

  Faculty Of Engineering University Of Tokyo

• Aizawa Kiyoharu

  Faculty Of Engineering University Of Tokyo

• Aizawa Kiyoharu

  Faculty Of Engineering The University Of Tokyo

• Ishizaki Toru

  Faculty of Engineering, University of Tokyo

• Ishizaki Toru

  Faculty Of Engineering University Of Tokyo

• Hatori Mitsutoshi

  Faculty Of Engineering The University Of Tokyo

• Li Zheng

  Faculty of Engineering, University of Tokyo

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• Evaluation of Fractal Image Coding (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
• センサ面上での2次元動きベクトル検出の提案と設計

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