A Power Reduction Technique for an Equalization Circuit Using Adaptive Bitwidth Control

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概要

• 論文の詳細を見る

• In this paper, we propose a new technique for a low power equalization circuit using adaptive bitwidth control. It can reduce the amount of necessary calculation to control the bitwidth of the equalization circuit. In the compensation step, estimation in equalizing will be held in the less bitwidth when the error signals are big. On the other hand, detailed calculation will be held in the more bitwidth when error signals are small. We show that our new technique is effective for a low power equalization circuit by experimental simulation while keeping the required calculation accuracy.

• 社団法人電子情報通信学会の論文
• 2004-06-11

著者

• Muroyama Masanori

  Graduate School Of Information Science And Electrical Engineering Kyushu University

• TARUMI Kousuke

  Graduate School of Information Science and Electrical Engineering, Kyushu University

• YASUURA Hiroto

  System LSI Research Center, Kyushu University

• Tarumi Kousuke

  Graduate School Of Information Science And Electrical Engineering Kyushu University

• Muroyama Masanori

  Graduate School of Information Science & Electrical Engineering, Kyushu University

関連論文

• Bitwidth Optimization for Low Power Digital FIR Filter Design(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
• A Power Reduction Technique for an Equalization Circuit Using Adaptive Bitwidth Control
• A Power Reduction Technique for an Equalization Circuit Using Adaptive Bitwidth Control
• A Power Reduction Technique for an Equalization Circuit Using Adaptive Bitwidth Control

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