Multi-Stage Fiber Delay Line Buffer in Photonic Packet Switch for Asynchronously Arriving Variable-Length Packets(Internet)

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概要

• 論文の詳細を見る

• We study photonic packet switches to support asynchronously arriving variable-length packets. A scheduler for contention resolution is operated in electrical domain even when data street of the buffer is provided in optical domain. In this scheme, the scheduler may be a bottleneck. To compensate the gap of high-speed optical transmission and slow-speed electronic processing, we propose a multi-stage fiber delay line (FDL) buffer architecture that forms a tree structure in which each node has a block of FDLs and a scheduler. This is especially useful for output-buffer switches in which scheduling complexity is proportional to the number of ports of the packet switch. Through a newly-developed approximate analytical method, we show the optimum unit length of the fiber delay lines to decrease packet loss probability. We also show the sufficient number of FDLs in the two-stage buffer.

• 社団法人電子情報通信学会の論文
• 2005-01-01

著者

• HARAI Hiroaki

  National Institute of Information and Communications Technology (NICT)

• Wada Naoya

  National Institute of Information and Communications Technology, New Generation Network Research Cen

• Harai Hiroaki

  National Inst. Of Information And Communications Technol.

• Harai Hiroaki

  National Institute Of Information And Communications Technology

• KUBOTA Fumito

  National Institute of Information and Communications Technology

• Wada Naoya

  National Inst. Information And Communications Technol. Tokyo Jpn

• Shinoda Yoichi

  Center For Information Science Japan Advanced Institute Of Science And Technology

• OGASHIWA Nobuo

  the School of Information Science, Japan Advanced Institute of Science and Technology

• Ogashiwa Nobuo

  The School Of Information Science Japan Advanced Institute Of Science And Technology

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