155-Mb/s Burst-Mode Clock Recovery Circuit Using the Jitter Reduction Technique

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概要

• 論文の詳細を見る

• We propose a simple technique for reducing the jitter of the output clock generated in the clock recovery circuit (CRC) for burst-mode data transmission. By using this technique, the proposed CRC based on the gated oscillator (GO) can recover the output clock with a low-jitter even when there are consecutive same data streams encountered in the system. The circuit is composed only of digital logic devices and can recover the input data errorless until 1,000 consecutive same data bits are incoming.

• 社団法人電子情報通信学会の論文
• 2003-04-01

著者

• Park Chang-soo

  Department Of Internal Medicine Chonnam National University Medical School

• Park Chul-soo

  Department Of Information And Communications

• HWANG Jae-Seung

  Department of Information and Communications

• Park Chul-soo

  Department Of Crop Science And Biotechnology Chonbuk National University

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