Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder

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概要

• 論文の詳細を見る

• This paper presents a hardware-efficient architecture of tree-depth scan (TDS) and multiple quantization (MQ) scheme for zerotrce coding in MPEG-4 still texture coder. The proposed TDS architecture can achieve its maximal throughput to area ratio and minimize the external memory access with only one wavelet-tree size on-chip buffer. The MQ scheme adopts the powcr-of-two (POT) quantization to realize a cost-effective hardware implementation. The prototyping chip has been implemented in TSMC 0.35★m CMOS 1P4M technology. This architecture can handle 30 4CTF (70-1 ★ 576) frames per second with five spatial scalability and five SNR scalability layers at 100MHz working frequency.

• 社団法人電子情報通信学会の論文
• 2003-02-01

著者

• Chang Hao-chieh

  Department Of Electrical Engineering National Taiwan Universitya

• Yang Zhong-lan

  Department Of Electrical Engineering National Taiwan Universitya

• LIAN Chung-Jr

  Department of Electrical Engineering,National Taiwan Universitya

• CHEN Liang-Gee

  Graduate Institute of Electronics Engineering,Department of Electrical Engineering.National Taiwan U

• Lian Chung-jr

  Department Of Electrical Engineering National Taiwan Universitya

• Chen Liang-gee

  Graduate Institute Of Electronics Engineering And The Department Of Electrical Engineering National

• Chen Liang-gee

  Graduate Institute Of Electronics Engineering Department Of Electrical Engineering.national Taiwan U

関連論文

• Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder
• Feature-Based Error Concealment for Object-Based Video(Multimedia Systems for Communications)

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