A 0.6-V Supply, Voltage-Reference Circuit Based on Threshold-Voltage-Summation Architecture in Fully-Depleted CMOS/SOI(Special Issue on High-Performance Analog Integrated Circuits)
スポンサーリンク
概要
- 論文の詳細を見る
A low-voltage silicon-on-insulator (SOI) voltage-reference circuit has been developed. It is based on threshold-voltage-summation architecture and the output is not affected by the input offset of the feedback amplifier. Thus, the output dispersion is considerably reduced. An undoped MOSFET is used as a depletion-mode transistor because of its small threshold voltage. The temperature dependence of normal and undoped MOSFETs in fully depleted CMOS/SOI technology is studied for designing a temperature-insensitive voltage-reference circuit. A prototype circuit, fabricated on a fully depleted CMOS/SIMOX process, has a measured reference voltage of 530 ± 16.8mV (3σ), and can operate at a supply voltage as low as 0.6 V. The measured temperature coefficient is 0.02 ± 0.06 mV/℃ (3σ).
- 社団法人電子情報通信学会の論文
- 2002-08-01
著者
-
Suzuki Kenji
Ntt Telecommunications Energy Laboratories
-
TSUKAHARA Tsuneo
NTT Telecommunications Energy Laboratories
-
Ugajin Mamoru
Ntt Telecommunications Energy Laboratories
関連論文
- 3 to 5-GHz Si-Bipolar Quadrature Modulator and Demodulator Using a Wideband Frequency-Doubling Phase Shifter (Special Section on Analog Circuit Techniques Supporting the System LSI Era)
- A Low-Voltage 6-GHz-Band CMOS Monolithic LC-Tank VCO Using a Tuning-Range Switching Technique(Special Section on Analog Circuit Techniques Supporting the System LSI Era)
- Suppression of Substrate Crosstalk in Mixed-Signal Complementary MOS Circuits Using High-Resistivity SIMOX(Separation by IMplanted OXygen)Wafers
- Suppression of Substrate Crosstalk in Mixed Analog-Digital CMOS Circuits by Using High-Resistivity SIMOX Wafers
- A 1-V 2-GHz RF Receiver with 49 dB of Image Rejection in CMOS/SIMOX(Special Section on Analog Circuit Techniques and Related Topics)
- A 0.6-V Supply, Voltage-Reference Circuit Based on Threshold-Voltage-Summation Architecture in Fully-Depleted CMOS/SOI(Special Issue on High-Performance Analog Integrated Circuits)