CMOS Embedded RAMs for Digital Communication Systems (Special Section on High Speed and High Density Multi Functional LSI Memories)

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概要

• 論文の詳細を見る

• This paper describes CMOS embedded RAMs we developed utilizing 1.3 μm and 0.8 μm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 μm process technology and developed a 4 kW×9 b singleport embedded RAM with 5 ns access time and 100 mW power dissipation during 32 MHz operation, and a 1 kW×9 b dualport embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

• 社団法人電子情報通信学会の論文
• 1994-08-25

著者

• Satoh Yoichi

  Hitachi Vlsi Engineering Corp.

• Mikami Yasuo

  The Telecommunications Division Hitachi Ltd.

• Mizukami Masao

  the Device Development Center, Hitachi Ltd.

• Kozaki Takahiko

  the Central Research Laboratory, Hitachi Ltd.

• Mizukami Masao

  The Device Development Center Hitachi Ltd.

• Kozaki Takahiko

  The Central Research Laboratory Hitachi Ltd.

関連論文

• CMOS Embedded RAMs for Digital Communication Systems (Special Section on High Speed and High Density Multi Functional LSI Memories)

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