A 10b 300MHz Interpolated-Parallel A/D Converter (Special Section on the 1992 VLSI Circuits Symposium)

概要

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This paper describes a monolithic 10-b A / D converter that realized a maximum conversion frequency of MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V_<be> matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within ±0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of -59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A / D converter has been implemented as a 9.0 × 4.2-mm^2 chip integrating 36K elements, which consumes 4.0 W using a 1.0-μm-rule, 25-GHz f_t, double-polysilicon self-aligned bipolar technology.
社団法人電子情報通信学会の論文
1993-05-25