A Unified Analysis of Four-Quadrant Analog Multipliers Consisting of Emitter and Source-Coupled Transistors Operable on Low Supply Voltage (Special Section on Low-Power and Low-Voltage Integrated Circuits)
スポンサーリンク
概要
- 論文の詳細を見る
Novel circuit design techniques for bipolar and MOS four-quadrant analog multipliers operable on low supply voltage are described. There are three design techniques for multipliers operable on low supply voltage. One is the transistor-size unbalance technique. Another is the bias offset technique. A third is the multitail technique. Bipolar and MOS four-quadrant analog multipliers proposed in this paper consist of transistor-pairs with different transistor sizes (i.e. emitter areas or gate W / L values are different), transistor-pairs with the same bias offset or multitail cells (i.e. quadritail cells and an octotail cell). Several kinds of squaring circuits consisting of such transistor-pairs are applied to the multipliers when the multiplication method is based on the quarter-square technique. These multipliers all have satisfiable multiplication characteristics with four-quadrant operations in analog signal processing, whether implemented in bipolar technology or implemented in MOS technology.
- 一般社団法人電子情報通信学会の論文
- 1993-05-25
著者
関連論文
- A Unified Analysis of Four-Quadrant Analog Multipliers Consisting of Emitter and Source-Coupled Transistors Operable on Low Supply Voltage (Special Section on Low-Power and Low-Voltage Integrated Circuits)
- Low Temperature Coefficient CMOS Voltage Reference Circuits (Special Section on High-Performance MOS Analog Circuits)
- A Dynamic Bias Current Technique for a Bipolar Exponential-Law Element and a CMOS Square-Law Element Usable with Low Supply Voltage (Special Section of Letters Selected from the 1994 IEICE Spring Conference)