Logic Optimization:Redundancy Addition and Removal Using Implication Relations(Special Issue on Test and Diagnosis of VLSI)

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概要

• 論文の詳細を見る

• The logic optimization based on redundancy addition and removal is one of methods which can deal with largescale logic circuits. In this logic optimization a few redundant elements are added to a logic circuit, and then many other redundant elements which are generated by the redundancy addition are identified and removed. In this paper an optimization method based on redundancy addition and removal using implication relations is proposed. The advantage of the proposed method is to identify removable redundant elements with short time, because the proposed method directly identifies redundant elements using implication relations from two illegal signal assignments which are produced by redundancy addition. The experimental results compared this method with another method show that this method is faster than the another method without declining the optimization ability.

• 社団法人電子情報通信学会の論文
• 1998-07-25

著者

• Ichihara Hideyuki

  The Authors Are With The Department Of Applied Physics Faculty Of Engineering Osaka University

• Ichihara Hideyuki

  The Author Is With The Dept.of Information Sciences Hiroshima City Univ.

• Kinoshita Kozo

  The Authors Are With The Department Of Applied Physics Faculty Of Engineering Osaka University

• Kinoshita Kozo

  The Author Is With The Faculty Of Informatics Osaka Gakuin University

関連論文

• Logic Optimization:Redundancy Addition and Removal Using Implication Relations(Special Issue on Test and Diagnosis of VLSI)
• On Processing Order for Obtaining Implication Relations in Static Learning

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